The present invention relates to image processing apparatus, methods and computer program products and, more particularly, to deblocking filter apparatus, methods and computer program products.
Many image processing systems use image data compressed by Standard Video Codec. In general, a video codec may use H.261, H.262, and H.263 recommended by the International Telecommunication Union (ITU) and codec standards of MPEG-1, MPEG-2, MPEG-3, and MPEG-4 recommended by the Motion Picture Experts Group (MPEG). Research and standardizing work for a H.264 video codec capable of embodying higher compression rates is currently in progress.
In a conventional video decoder system shown in FIG. 1, encoded image data are restored to original data through a decoding procedure in an image processor and are displayed on a screen. Referring to FIG. 1, the conventional video decoder system includes a syntactic analyzer 102, a plurality of hardware modules 104, 106, 108, and 110 for decoding encoded image data, a memory 712, and peripheral devices DMA. These components exchange data transmission through a bus 120. As examples of the hardware modules, there is shown an entropy decoder 104, an inverse transformer 106, a predictor 108, and a deblocking filter 110. The encoded image data are sequentially processed by respective hardware modules and restored to original data. During a decoding procedure, corresponding modules access and read out data from an internal memory 112, such as an external memory or an SRAM, or store processed data therein.
Image data is compressed in macro blocks. When image data is restored to original data, a blocking effect may occur that produces different screens in macro blocks at boundaries between blocks of restored image data due to discontinuity of a slope or an image data value. The blocking effect appears as a square lattice along boundaries between blocks that can be easily sensed, causing a deterioration of subjective image quality. The deblocking filter 110 functions to reduce the blocking effect.
FIG. 2 is a block diagram that illustrates an operation of a deblocking filter 110. The deblocking filter 110 selects edges in which a filtering operation is to be performed (step S210), reads pixel data of a corresponding edge from the external memory 200 or an internal memory 112, and stores the read pixel data in a register array 204 of the deblocking filter 110 (step S212). The deblocking filter 110 keeps an edge part of a real image, and decides a filtering strength of a boundary filter to prevent excessive filtering (step S214). The deblocking filter 110 compares the filtering strength of a boundary filter with a threshold value, and finally judges whether or not a filtering operation is performed according to the compared result (step S216). When the filtering operation is performed, the deblocking filter 110 performs the filtering operation using pixel data of a corresponding edge stored in a register array 204 (step S218). Pixels from the filtering operation are output to an external recipient. An algorithm for such a deblocking procedure is described in H.264/AVC standards.
Because compression of image data in macro blocks can cause the blocking effect, an edge filtering in the deblocking filter may also be performed in macro blocks. FIG. 3 is a view that illustrates a filtering operation for one macro block. Referring to FIG. 3, a filtering operation for a current macro block is carried out based on a macro block A positioned at the left of the current macro block (MB) and a macro block B positioned above the current macro block. For an edge filtering of the current macro block, data for the macro block A and data for the macro block B are used.
Filtering operations for both a luminance component and a chroma component of pixels may be performed. FIG. 4A is a view showing a filtering operation sequence of a luminance component for one macro block. FIG. 4B is a view showing a filtering operation sequence of a chroma component for one macro block.
A macro block typically includes a 16×16 block of pixels. As shown in FIG. 4A, in a filtering operation of a luminance component for one macro block, filtering operations for 4 vertical boundaries and 4 horizontal boundaries are sequentially performed. Namely, a filtering operation of a luminance component is carried out in the order of a, b, c, d, e, f, g, and h. As shown in FIG. 4B, in a filtering operation of a chroma component for one macro block, a filtering operation for vertical boundaries i and j, and horizontal boundaries k and l are sequentially performed in a two-by-two manner. In general, after a filtering operation for a luminance component is performed, a filtering operation for a chroma component is carried out.
FIG. 5A is a view showing pixels used when one filtering operation for one vertical boundary is performed. FIG. 5B is a view showing pixels used when one filtering operation for one horizontal boundary is performed. As shown in FIGS. 5A and 5B, a filtering operation for one vertical boundary is performed over four pixels left and right. In the same manner, a filtering operation for one horizontal boundary is performed over four pixels up and down.
During a conventional filtering operation, particularly, when a filtering operation of a vertical component for a horizontal boundary is performed, because eight up-and-down pixels are accessed and the operation performed thereon, eight memory accesses may be required for each filtering operation. In order to perform the filtering operation of a vertical component for one macro block, a total of 768 cycles may be required. Thus, a time delay may occur in a filtering operation for image data having high quality. As a result, real-time processing of image data of high quality may be difficult.